Senior IC Layout Engineer

 

Position Overview:

Halo Microelectronics, a developer of analog and power management integrated circuits enabling energy-efficient smart systems is looking for an experienced Senior IC Layout Engineer to join the team.

As part of the engineering team, the Senior IC Layout Engineer will lead the IC layout for high-end analog and with a thorough understanding of the critical matching and routing issues working with the design team to floorplan layouts and achieve the best possible results. S/he will also assist design engineers with parasitic extraction.

Responsibilities:

  • Floorplan, layouts, and verification of high-end analog circuits using excellent knowledge of Cadence schematic layout and verification tools
  • Layout die using techniques to achieve best matching and performance
  • Work closely with circuit design engineers to ensure top quality and best performance
  • Provide best-in-class analog layouts that meet cost and performance targets while utilizing the latest tools, lessons learned, and best practices to achieve first-pass design success
  • Challenging layout projects that push the performance of the process technology and demand innovative solutions to complex design issues

Qualifications:

  • Must be able to work independently, maintain Cadence database, and management of own time and workload
  • Must be able to work in a team environment
  • Personal character and team-building skills essential to enabling on-time delivery of devices
  • Sharing of information with other team members and mentoring other layout designers less skilled or knowledgeable
  • Must demonstrate good communication and interpersonal skills
  • Must be able to perform as a team member

Minimum Requirements:

  • Bachelor’s degree in Electrical Engineering or related field with 5+ years experience
  • Thorough knowledge of high-end custom analog layout techniques
  • Must have thorough knowledge and understanding of device matching, Cadence layout tool, and top-level floor planning
  • Expert in high-end analog layout and possess a basic knowledge of semiconductor processing and design theory
  • Knowledge of Cadence OA software and Design Sync tools a plus
  • Freedom to pursue innovation in a rapidly changing market space

Location:

Singapore or Shanghai, China